In a computer system, a processor generally uses one or more timers to manage the forward progress of the work performed by the processor. The processor sets a timer so that the timer generates an interrupt at a desired point in time in the future.
In multiprocessor computer systems, including processing devices with multiple cores, there are generally two types of timers: per-processor timers and platform timers. A platform timer represents an instance of a timer that is shared among processors and can be accessed from any processor. A per-processor timer is an instance of a timer that is manipulated primarily by its respective processor.
From a power management point of view there also are two types of timers: timers that can be powered down and timers that are always on. A timer that can be powered down generally loses context when there is a power transition. A timer that is always on maintains context through power transitions.
When a processor is powered down, such as when the processor is entering a context-losing idle state, a per-processor timer that is not always-on will be stopped. In order for the processor to continue to monitor system status in the idle state, so as to identify a condition that results in becoming active again, a platform, always-on timer is used by that processor to maintain context. However, a platform timer generally can be controlled by only one processor at a time. Thus, in a multiprocessor system, when all processors have entered context-losing idle states, one processor programs the always-on platform timer to identify any condition that results in one or more processors becoming active again.